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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Features
* 2.488Gb/s 1:16 Demultiplexer * Fully Integrated Clock and Data Recovery * Single 3.3V Supply Operation * Differential LVPECL Low Speed Interface
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
* Maintains Clock Output in the Absence of Data * Loss of Lock, Loss of Signal Indicators * 128 Pin 14x20x2 mm Enhanced PQFP Pkg. * 2.3W Max Power Dissipation
General Description
The VSC8166 demultiplexes a 2.488Gbp/s LVPECL serial input datastream (DI+) to 16-bit wide, LVPECL 155Mb/s parallel data outputs (D0:D15+) for SONET/SDH applications. It has an integrated clock and data recovery unit with an on-chip PLL that internally generates a 2.488GHz clock in phase with the incoming data. Internal divider circuits are used to take the high-speed clock and generate 155.52MHz (CLK16O+) and 77.76MHz (CLK32O+) LVPECL external output clocks. The incoming data is retimed and demultiplexed to a 16-bit word which is clocked out of the demultiplexer by the 155.52MHz output clock. Alarm functions support typical telecom system applications. A TTL Loss Of Lock (LOL) indicator can be externally enabled (LOLEN) to detect when the device goes out of lock, which would most often occur in the event of a loss of valid data. A TTL No-Reference (NOREF) output indicator flags when the LVPECL Clock Reference (REFCLK) input to the VSC8166 either is removed, or goes severely out of tolerance. For Loss Of Signal (LOS) conditions from an Optics Module, the VSC8166 provides a polarity (POL) input to accommodate any polarity differences. Only a single 3.3V power supply is required for device operation and the device is packaged in a thermally enhanced 128 Pin 14x20x2 mm PQFP Package.
VSC8166 Block DIagram
D0+ D0Output Register 1:16 DMUX
DI+ DIREFCLK+ REFCLK-
Data Re-time Clock Recovery Divide by 16
D15+ D15CLK16O+ CLK16O-
POL LOS LOLEN Divide by 2
CLK32O+ CLK32ONOREF LOL
1 0
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Functional Description
Clock Recovery: The incoming SONET/SDH data stream is fed both to a re-timing latch and to the integrated clock recovery unit (CRU). The CRU exceeds the SONET/SDH jitter tolerance map. A 77.76MHz reference clock (REFCLK+) is required for CRU operation. Off-chip termination of this input is required. For AC coupling, a bias voltage suitable for AC coupling needs to be provided, see Figure 1 for biasing scheme. The 77.76MHz reference is used to permit the CLK16O+ to remain locked to this external reference clock in the event of data loss. Figure 1: AC Termination of LVPECL REFCLK Input Chip Boundary
VCC = 3.3V
Split-end equivalent termination is Zo to VTerm R1 = 125, R2 = 83, Zo=50, VTerm= VCC-2V R1||R2 = Zo VCCR2 + VEER1 = VBias
VCC
R1 ZO CIN R2
R1+R2
VEE VCC
R1 ZO CIN R2
VEE
VEE = 0V
CIN TYP = 100 nF for AC operation.
The VSC8166 has a TTL input LOS to force the part into a Loss of Signal state. Most optics have a TTL output usually called "SD" (Signal Detect), based on the optical power of the incoming light stream. Depending on the optics manufacturer, this signal is either active high or low. To accommodate polarity differences, the internal Loss of Signal is generated when the POL and LOS inputs are of opposite states. Once active, all zeroes "0" will be propagated downstream using the transmit clock until the optical signal is regained and LOS and POL are in the same logic state. When LOS and POL are opposite logic states, an internal LOS is asserted and all output data D(0:15)+ will go to zero on the next rising edge of CLK16O+. If LOLEN is low, and the serial input data consists of 3.3us or more of continuous zeros, LOL will go high and remain high for 100us following the restoration of valid data. If LOLEN is high, loss of data lock "OR" 3.3us of zeros will cause LOL to go high and remain high for 100us after both the return of non-zero data, and phase locking of the Serial data and clock are obtained. NOREF will go high asynchronously when REFCLK is lost, or when REFCLK is not locked to the internal 2.488GHZ clock. It will remain high until the condition is corrected.
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Low Speed Interface The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D(15:0)+ with accompanying differential LVPECL divide by 16 clock CLK16O and divide by 32 clock CLK32O. The low speed LVPECL output drivers are designed to drive a 50 transmission line. The transmission line can be DC terminated with a split end termination scheme, see Figure 2, or DC terminated by 50 to VCC-2V on each line, see Figure 3. At any time, the equivalent split-end termination technique can be substituted for the traditional 50 to VCC-2V on each line. AC coupling can be achieved by a number of methods. Figure 4 illustrates an AC coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the downstream device were to have internal termination, the line to line 100 resistor may not be necessary. The divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163. Figure 2: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
Split-end equivalent termination is Zo to VTerm VCC R1 = 125 R2 = 83, Zo=50, VTerm= VCC-2V
R1
R1
Zo
downstream
R1||R2 = Zo VCCR2 + VEER1 R1+R2
Zo R2
= VTerm
R2
VEE
Figure 3: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
downstream
Zo
R1 =50 VCC-2V
R1 =50 VCC-2V
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Figure 4: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
Zo Zo 50 50
0.1uF
downstream
bias point generated internally
0.1uF
VCC-2V
High Speed Interface The incoming 2.488Gb/s data is received by high speed inputs DI+. The data inputs are internally terminated by a center-tapped resistor network. For differential input DC coupling, the network is terminated to the appropriate termination voltage VTERM (pins HSDREF) providing a 50 to VTERM termination for both true and complement inputs. For differential input AC coupling, the network is terminated to VTERM via a blocking capacitor. In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. Serial data inputs have the circuit topology shown in Figure 5. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude (VCMI, VIHS). For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either side of the differential gate.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Figure 5: High Speed Serial Data Inputs Chip Boundary
VCC = 3.3V
ZO
CIN
50
CAC VTerm CIN ZO
50
VEE = 0V
CIN TYP = 100 pF CAC TYP = 100pF
Supplies This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be 3.3V. Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should also be placed in parallel with the 0.1F and 0.01F capacitors mentioned above. Recommended capacitors are low inductance ceramic SMT X7R devices. For the 0.1F capacitor, a 0603 package should be used. The 0.01F and 0.001F capacitors can be either 0603 or 0403 packages. For low frequency decoupling, 47F tantalum low inductance SMT caps should be sprinkled over the board's main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
AC Characteristics
Figure 6: AC Timing Waveforms
CLK16O+
Parallel data clock output tpdd
D(0...15)+
Parallel data outputs
VALID DATA (1)
VALID DATA (2)
CLK32O+
Parallel data clock output
tpd32
DI+
High speed differential serial data input
D0
D1 D2
D3 D4
D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b a b
Single Ended Swing
=
= a * Differential swing () is specified as | b - a | (or | a - b |), as is the single ended swing. Differential swing is specified as equal in magnitude to single ended swing.
Differential Swing
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Table 1: AC Characteristics Parameters tpdd tpd32 tDR, tDF tCLKR, tCLKF tCLKR32, tCLKF32 CLK16OD Description Data valid from falling edge of CLK16O+ CLK32O transition from falling edge of CLK16O+ D[15:0]+/- rise and fall times CLK16O+/- rise and fall times CLK32O+/- rise and fall times CLK16O+/- duty cycle distortion
45
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Min
0 0
Max
1.0 1.0 400 400 400
Units
ns ns ps ps ps % of clock cycle
Conditions
20% to 80% into 50 Ohm load See Figure 7 20% to 80% into 50 Ohm load See Figure 7 20% to 80% into 50 Ohm load See Figure 7
55
Table 2: DC Characteristics (Over recommended operating conditions). Parameters VOH VOL
VOLVPECL VIHS VCMI
Description PECL output high voltage PECL output low voltage Low speed output voltage differential peakto-peak swing. Serial input differential (DI+/-) Serial input common mode voltage Supply voltage Power dissipation Supply Current
Min
VCC-1.02 VCC2.00 400
Typ
Max
VCC-0.70 VCC-1.62
Units
V V
Conditions 50 Termination to VCC 2.0V, See Figure 7 50 Termination to VCC 2.0V, See Figure 7 50 Termination to VCC 2.0V, See Figure 7 AC Coupled, internally biased to (VCC+VEE)/2
1200
mV
400 VCC-1.5 3.14 -- -- -- 1.7 525
1200 VCC-0.5 3.47 2.3 660
mV V V W mA
VCC
PD IDD
3.3V 5% Outputs open, VCC = 3.45V Outputs open, VCC = 3.45V
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Figure 8: Parametric Measurement Information
PECL Rise and Fall Time
80% 20%
Parametric Test Load Circuit PECL Output Load
Z0 = 50
50 VCC-2.0V
Tr
Tf
Absolute Maximum Ratings (1)
Power Supply Voltage, (VCC)....................................................................................................... -0.5V to +3.8V DC Input Voltage (Differential inputs) ................................................................................... -0.5V to Vcc+0.5V Output Current (Differential Outputs)....................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55o to +125oC Storage Temperature.................................................................................................................. -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................1500V
Recommended Operating Conditions
Power Supply Voltage, (VCC)..............................................................................................................+3.3V+5% Operating Temperature Range ...........................................................0oC Ambient to +85oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8166 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V.
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Package Pin Descriptions
Table 3: Package Pin Identification Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Name
NC NC CLKREF VCC VEE_CMU VEE_CMU VEE_CMU VCC_CMU REFCLK+ REFCLKVCC_CMU VCC DI+ DIVEE VEE VEE VCC HSDREF NC VCC NC VCC VCC VCC VEE VEE VEE VEE VEE NC NC NC NC
I/O
-- -- I/O -- -- -- -- -- I I -- -- I I -- -- -- -- I -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Level
-- -- 0V or 1.3V 3.3V typ. GND typ. GND typ. GND typ. 3.3V typ. LVPECL LVPECL 3.3V typ. 3.3V typ. LVPECL LVPECL GND typ. GND typ. GND typ. 3.3V typ. 0V or 1.3V -- 3.3V typ. -- 3.3V typ. 3.3V typ. 3.3V typ. GND typ. GND typ. GND typ. GND typ. GND typ. -- -- -- --
Description
No connect, leave unconnected No connect, leave unconnected Reference clock input termination voltage. 1.3V for DC coupling, otherwise 0V. Positive power supply pin Negative power supply for CMU Negative power supply for CMU Negative power supply for CMU Positive power supply for CMU Reference clock input, true. Reference clock input, complement. Positive power supply for CMU Positive power supply pin High speed data input, true High speed data input, complement Negative power supply pin Negative power supply pin Negative power supply pin Positive power supply pin High speed data input termination voltage reference. 1.3V for DC coupling, otherwise 0V. No connect, leave unconnected Positive power supply pin No connect, leave unconnected Positive power supply pin Positive power supply pin Positive power supply pin Negative power supply pin Negative power supply pin Negative power supply pin Negative power supply pin Negative power supply pin No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Table 3: Package Pin Identification Pin #
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Preliminary Datasheet
VSC8166
Name
NC NC NC NC VCCT VEET NC VEE VCC LOLEN NC NC NC NC NC VCC VEE REFCK_TEST NC VCC LOS POL VEE D15+ D15VCC D14+ D14NC VCC NC VCC D13+ D13VEE
I/O
-- -- -- -- -- -- -- -- -- I -- -- -- -- -- -- -- -- -- -- I I -- O O -- O O -- -- -- -- O O --
Level
-- -- -- -- +3.3V typ. GND typ. -- GND typ. 3.3V typ. TTL -- -- -- -- -- 3.3V typ. GND typ. GND typ. -- 3.3V typ. TTL TTL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL -- 3.3V typ. -- 3.3V typ. LVPECL LVPECL GND typ.
Description
No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected TTL VCC Power Supply TTL VEE Power Supply No connect, leave unconnected Negative power supply pin Positive power supply pin Loss of Lock enable. LOLEN= "1": LOL asserts high when loss of data OR 3.3S of zeroes, LOLEN="0": LOL assets high when 3.3S of zeroes No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected Positive power supply pin Negative power supply pin Test input signal used for production test. Active high. Connect to ground for normal operation. No connect, leave unconnected Positive power supply pin Loss of Signal control Polarity Signal Control Negative power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment No connect, leave unconnected Positive power supply pin No connect, leave unconnected Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Negative power supply pin
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Table 3: Package Pin Identification Pin #
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Name
D12+ D12VCC D11+ D11VCC D10+ D10VEE D9+ D9VCC D8+ D8VCC D7+ D7VEE D6+ D6VCC D5+ D5VCC D4+ D4VEE D3+ D3VCC D2+ D2VCC VCC NC D1+ D1-
I/O
O O -- O O -- O O -- O O -- O O -- O O -- O O -- O O -- O O -- O O -- O O -- -- -- O O
Level
LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. 3.3V typ. -- LVPECL LVPECL
Description
Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Negative power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Negative power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Negative power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Low speed differential parallel data, true Low speed differential parallel data, compliment Positive power supply pin Positive power supply pin No connect, leave unconnected Low speed differential parallel data, true Low speed differential parallel data, compliment
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Table 3: Package Pin Identification Pin #
107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Preliminary Datasheet
VSC8166
Name
VCC D0+ D0VEE CLK16OCLK16O+ VCC CLK32OCLK32O+ NC NOREF VCCT VEEY LOL NC VEE VCC NC NC VEE VEE VCC
I/O
-- O O -- O O -- O O -- O -- -- O -- -- -- -- -- -- -- --
Level
3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL -- TTL 3.3V typ. GND typ. TTL -- GND typ. 3.3V typ. -- -- GND typ. GND typ. 3.3V typ. Positive power supply pin
Description
Low speed differential parallel data, true Low speed differential parallel data, compliment Negative power supply pin Parallel clock output, complement Parallel clock output, true Positive power supply pin Divided Parallel clock output, complement Divided Parallel clock output, true No connect, leave unconnected No reference clock output. Active high for REFCLK missing or severely out of tolerance. Positive power supply pin (TTL) Negative power supply pin (TTL) Loss of lock indicator. No connect, leave unconnected Negative power supply pin Positive power supply pin No connect, leave unconnected No connect, leave unconnected Negative power supply pin Negative power supply pin Positive power supply pin
Note: No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device.
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Package Information
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
128 PQFP Package Drawings
PIN 128 PIN 1 PIN 102
Key
RAD. 2.92 .50 (2)
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A A1 A2
E1 E
D D1 E
EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK
2.54 .50
E1 L e b R R1
PIN 38 D1 D TOP VIEW 10 TYP.
PIN 64
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
0.17
MAX.
b
LEAD COPLANARITY
NOTES:
L
Package #: 101-322-5 Issue #: 2
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Package hermal Considerations
This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table
Table 4: Thermal Resistance Symbol
jc ja
Description
Thermal resistance from junction to case. Thermal resistance from junction to ambient with no airflow, including conduction through the leads.
C/W
2.2
23.9
Thermal Resistance with Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 5: Thermal Resistance with Airflow Airflow
100 lfpm 200 lfpm 400 lfpm 600 lfpm
ca (oC/W)
19.8 16.7 14.6 13.0
Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation:
T A ( MAX ) = T C ( MAX ) - P ( MAX ) CA
where: A(MAX) Ambient Air temperature C(MAX) Case temperature (85oC for VSC8166) P(MAX) Power (2.3W for VSC8166) CA Theta case to ambient at appropriate airflow The results of this calculation are listed below:
Page 14
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Airflow
none 100 lfpm 200 lfpm 400 lfpm 600 lfpm Max Ambient Temp oC 29.6 39.5 46.6 51.4 55.1
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Table 6: Maximum Ambient Air Temperature without Heatsink
Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow.
Notice
This document contains preliminary information about a new product in the preproduction phase of development. The information in this document is based on initial product characterization. Vitesse reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availability of the product at any time. The reader is cautioned to confirm this datasheet is current prior to using it for design.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52252-0, Rev. 3.0
11/9/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52252-0, Rev 3.0 11/9/99

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